Example embodiments disclosed herein relates to flash memory devices and more particularly, to a multi-chip flash memory device and method for reading status data therefrom.
In recent years, the application fields for volatile and nonvolatile memories have been spreading rapidly over mobile apparatuses such as MP3 players, personal multimedia players (PMP), mobile phones, notebook computers, personal digital assistants (PDA), and so on. Those mobile apparatuses may require storage units with great storage capacity in order to provide for various functions (e.g., playing motion pictures). Thus, there have been many studies related to these requirements, some of which are ongoing even today. One of those efforts involves a scheme of multi-chip package in which pluralities of memory devices may be constructed in a single package. The multi-chip package may be useful for reducing the package size for a given memory capacity remarkably by stacking memory chips of the same kind on a board. Generally, a plurality of memory chips included in a multi-chip package may share an input/output bus and control pins. But, the memory chips may be able to independently conduct their own programming or erasing operations. For those operations, there may be a need for a memory controller to manage the memory chips individually and enable an external system or host to identify them as a single device.
Recent flash memory devices may embed memory controllers for conducting the sequences of programming and erasing operations therein. In those flash memory devices, when commands and program data are input from external systems, series of operations may be automatically carried out until programming operations, including writing and verifying operations with data, are complete. In the programming and erasing operations, a ready/busy signal (Rn/B) may be output from the beginning to the end of operation, inhibiting an access to the memory. But, in a multi-chip flash memory device where pluralities of flash memory chips are embedded in a single package, all of the memory chips may not be fully engaged in a programming or erasing operation at the same time. Therefore, the memory chips may provide the ready/busy signals to an external host at different points in response to commands identified each by the memory chips. In other words, the ready/busy signals of the memory chips may be output in time-divisional mode by the commands provided in time-divisional mode. Generally, the memory chips output the ready/busy signals to input/output (I/O) pins that may be used as input/output terminals.
FIG. 1 is a timing diagram briefly showing an output pattern of ready/busy signals Rn/B in a general multi-chip flash memory device. Referring to FIG. 1, the general multi-chip flash memory device outputs the ready/busy signals Rn/B in the time-divisional mode as aforementioned. Commands for outputting the ready/busy signals Rn/B are provided to each of the memory chips in different points.
If storing a large capacity of data, the multi-chip flash memory device may operate in the interleaved mode in which all of the memory chips continuously conduct programming operations with data provided thereto. In this case, a host or memory controller may frequently request the ready/busy signals Rn/B from each of the memory chips in order to check on states of the programming operations. In such a general multi-chip flash memory device outputting the ready/busy signals Rn/B in the time-divisional mode, those frequent requests may be provided with commands that are exclusively identified by each of the memory chips. Namely, the commands for requesting the ready/busy signals may be assigned such that one memory chip identifies a command requesting the ready/busy signal Rn/B while other memory chips cannot identify the command. The host or memory controller may provide the memory chips with the commands for requesting the ready/busy signals Rn/B and then may receive the ready/busy signal Rn/B for predetermined clock cycles. If there is a need to request the ready/busy signals Rn/B from all of the memory chips, these operations may be carried out independently on the memory chips. Then, after inputting the commands to the memory chips and confirming conditions of the ready/busy signals Rn/B output from each of the memory chips, the host or memory controller may terminate the status check operations if the memory chips. If the status check operations for the ready/busy conditions of the memory chips are terminated, the host (or memory controller) may select a memory chip to be programmed and provide program data (i.e., data to be programmed) to the selected memory chip. According to an output pattern of the ready/busy signals Rn/B by the time-divisional mode, the ready/busy signal Rn/B may be assigned to a data bit output through one of input/output pins I/O<n−1:0> which are controlled by toggling operations of a output-enable (or read-enable) signal nRE. For instance, I/O<1> among n-bit data output in a one clock cycle may be assigned to the ready/busy signal Rn/B. Therefore, in order to provide the ready/busy status of all memory chips to the host, the host or memory controller may be required to apply respective commands to each of the memory chips at different points and obtain the ready/busy signals Rn/B at different points. However, for a programming operation with a large amount of data (i.e., an interleaved programming operation in the multi-chip flash memory device), the host or memory controller may need to frequently request the ready/busy signals Rn/B from all of the memory chips included in the multi-chip flash memory device. Those frequent requests and outputs with the ready/busy signals Rn/B may consume a significant amount of time. Further, if it is impossible to find an internal operation state of a memory chip in a short time, a fast interleaved programming operation may be more difficult to accomplish. A longer standby time for confirming the ready/busy signals Rn/B of the multi-chip flash memory device may degrade the operation rate of the memory system.
Techniques for controlling outputs of the ready/busy signals Rn/B in the multi-chip flash memory device are disclosed in related art. But, the related art does not suggest an art capable of shortening a standby time for the ready/busy signals Rn/B provided from each of a plurality of memory chips. Reducing the output standby time of the ready/busy signals Rn/B may improve the efficiency and data rate of the interleaved operation in the multi-chip flash memory device.